00628nam a2200205 a 4500 PK-NaQUE 20260518125056.0 260518b |||||||| |||| 00| 0 eng d 0132599708 (paperback) 9780132599702 (paperback) QUEST Palnitkar, Samir. Verilog HDL: a guide to the digital design and synthesis 2nd ed. [S.l.] : Prentice Hall, 2003. 496 p. ; Verilog (Computer hardware description language) http://10.10.170.122:8080/browse/book/2556 Download eBook BK ddc 6662 6662 0 0 0 0 QUESTCL QUESTCL 2014-06-14 878.00 1 621.395PAL 43723 2017-12-04 00:00:00 2017-05-16 2014-06-14 BK with CD 0 0 0 0 QUESTCL QUESTCL 2014-06-14 878.00 1 621.395PAL 43724 2017-01-04 00:00:00 2016-07-27 2014-06-14 BK with CD 0 0 0 0 QUESTCL SLES 2014-06-14 878.00 0 621.395PAL 43725 2014-06-14 00:00:00 BK 0 0 0 0 QUESTCL SLES 2014-06-14 878.00 0 621.395PAL 43726 2014-06-14 00:00:00 BK 0 0 0 0 QUESTCL SLES 2014-06-14 878.00 0 621.395PAL 43727 2014-06-14 00:00:00 BK 0 0 0 0 LFG LFG 2014-10-01 385.00 0 621.395PAL 32774 2014-10-01 00:00:00 BK 0 0 0 0 QUESTCL QUESTCL 2014-10-01 385.00 0 621.395PAL 32775 2014-10-01 00:00:00 2014-10-01 BK 0 0 0 0 QUESTCL QUESTCL 2014-10-01 385.00 0 621.395PAL 32776 2014-10-01 00:00:00 2014-10-01 BK 0 0 0 0 QUESTCL QUESTCL 2014-10-01 385.00 0 621.395PAL 32777 2014-10-01 00:00:00 2014-10-01 BK 0 0 0 0 QUESTCL QUESTCL 2014-10-01 385.00 0 621.395PAL 32778 2014-10-01 00:00:00 2014-10-01 BK 0 0 0 0 QUESTCL QUESTCL 2014-06-19 700.00 0 621.38153PAL 33703 2026-05-18 12:43:46 2026-05-18 BK 0 0 0 0 LFG LFG 2014-06-19 700.00 0 621.38153PAL 33704 2026-05-18 12:43:46 2026-05-18 BK 0 0 0 0 QUESTCL QUESTCL 2014-06-19 700.00 0 621.38153PAL 33705 2026-05-18 12:43:46 2026-05-18 BK 0 0 0 0 QUESTCL QUESTCL 2014-06-19 700.00 0 621.38153PAL 33706 2026-05-18 12:43:46 2026-05-18 BK 0 0 0 0 QUESTCL QUESTCL 2014-06-19 700.00 0 621.38153PAL 33707 2026-05-18 12:43:46 2026-05-18 BK